In conventional receivers, an analog gain control (AGC) loop is used to measure the instantaneous power as well as the average power received by an analog-to-digital converter (ADC). Based on the average power, the gain of the analog circuitry is adjusted such that the input to the ADC will stay within its predetermined dynamic range. In such conventional receivers, gain is controlled by a feedback loop which causes an undesired delay when adjusting the gain.
As shown in FIG. 1, a conventional radio frequency (RF) receiver 100 includes an analog radio receiver 102, at least one analog-to-digital converter (ADC) 104, and an analog gain control loop that measures the instantaneous power as well as the average power. The analog gain control loop includes a power estimator 106, a loop filter 108 (e.g., an LPF), a summer 110, a lookup table (LUT) 112, a digital-to-analog converter (DAC) 114 and a gain control circuit 116. The summer 110 adds a reference signal having a predetermined value −Pref to the output of the loop filter. The error voltage at the output of the summer 110 becomes zero when the average input power reaches the value of Pref.
The analog radio receiver 102 is a direct conversion receiver which includes an antenna 125 for receiving a wireless communication signal, a bandpass filter 130, a low noise amplifier (LNA) 135, an optional second filter 140 (e.g., bandpass filter), a demodulator 145 having two outputs 150, 155, a phase-locked loop (PLL) 160, an analog real signal path low pass filter (LPF) 165A, an analog imaginary signal path LPF 165B, at least one real signal path amplifier 170A, at least one imaginary signal path amplifier 170B, at least one analog real signal path high pass filter (HPF) circuit 175A, and at least one analog imaginary signal path HPF circuit 175B. Each of the amplifiers 170A, 170B, includes a high gain stage residing in the analog domain of the RF receiver 100.
The PLL 160 generates a local oscillator (LO) signal to control the two outputs 150, 155 of the demodulator 145. The output 150 is an in-phase (I) output of the demodulator 145 for outputting a real signal component of the wireless communication signal. The output 155 is a quadrature (Q) output of the demodulator 145 for outputting an imaginary signal component of the wireless communication signal. The analog LPFs 165A, 165B, control the bandwidth selectivity of the I and Q outputs 150 and 155, respectively. The outputs of the analog LPFs 165A, 165B, are then amplified by the amplifiers 170A, 170B, respectively.
Due to high gain requirements, the analog HPF circuits 175A, 175B, are included in the analog radio receiver 102 to provide capacitance after each of the amplifiers 170A, 170B, respectively, whereby the amplifiers 170A, 170B, are AC-coupled and any residual direct current (DC) is removed to prevent DC offset. Each of the analog HPF circuits 175A, 175B, has a signal input, a signal output, at least one capacitor C1, C2, which connects the signal input to the signal output, and at least one resistor R1, R2, which connects the output of the capacitor to ground, thus forming an R-C filter. The analog HPF circuits 175A, 175B, alter the spectral shape (i.e., reducing the energy) of the lower portion (e.g., below 50 kHz) of the frequency domain response associated with the real and imaginary signal components.
In the conventional RF receiver 100 of FIG. 1, the ADC 104 is connected to the output of the analog HPF circuits 175A, 175B. The analog HPF circuits 175A, 175B, are utilized to guarantee the spectral shape of the wireless communication signal received via the antenna 125 before being sampled at the ADC 104. The ADC 104 outputs digital I and Q outputs 180, 185, to the power estimator 106 which, for example, performs a function in which I2+Q2 is calculated.
In the RF receiver 100, the reaction time necessary to adjust the gain of the amplifiers 170A, 170B, to respond to large changes in the gain of signals received at the antenna 125 is considerable. The gain adjustment of the amplifiers 170A, 170B, is based on a feedback loop which includes a power estimator 106, a loop filter 108, a summer 110, look up table (LUT) 112, a digital-to-analog converter (DAC) 114 and a gain control circuit 116. A reference power (PREF) value is subtracted from the output of the loop filter via the summer 110 to generate an error signal 118. Based on the error signal 118, the LUT 112 sets the DAC 114 to a predetermined setting such that the gain control circuit 116 adjusts the gain of the amplifiers 170A, 170B accordingly. Furthermore, because the potential range of the input signal variation received at the antenna 125 of the analog radio receiver 102 may be very large (e.g., a 75 dB dynamic range), a very large capacity and expensive ADC 104 (e.g., having 13 bits whereby 6 dB dynamic range is provided per bit) is required. The ADC 104 will also consume considerable power.
It is desirable to provide a method of addressing DC offset cancellation and gain control without the disadvantages addressed above.